1. Field of the Invention
The invention disclosed and claimed herein generally pertains to a method for providing a set of test patterns or test vectors for use in scan testing an integrated circuit or other microelectronic component. More particularly, the invention pertains to a method of the above type wherein non-linear compression is used, in connection with a random pattern generator that is operated to provide the test patterns. Even more particularly, the invention pertains to a method of the above type that uses multiple non-linear encoding schemes for data compression, and thereby allows the random pattern generator to be of reduced size.
2. Description of the Related Art
As is known by those of skill in the art, Design for Testability (DFT) refers to certain design techniques, wherein features are added to an integrated circuit (IC) or other microelectronic hardware for use in testing data. In a DFT technique known as scan testing, a scan enable signal is added to the design of an IC chip. When this signal is asserted, respective flip-flops or latches in the IC are connected together to form one or more shift registers, wherein each register has an input pin and an output pin. Using the clock signal of the IC, pre-selected patterns of test vectors can be entered into the chain of flip-flops, and the state of every flip-flop is then read out. Thus, a substantial set of test output data is generated, such as a data set comprising 1,000 or 2,500 bits. This output data is thereby made available for analysis, in order to detect the presence of faults in the IC. As is well known, the input test patterns are typically designed or customized to a particular IC chip. A pseudorandom generator is a common device used for producing the required test patterns.
As is further well known, while an input test pattern may comprise logic 1's or 0's at 1,000 bit positions, only the logic values at a comparatively small number of bit positions, such as 50 or 100 positions, will typically be important for a particular scan test procedure. These important bits or bit positions are referred to herein as specified bits. The logic values at all of the other positions do not matter. Accordingly, the term “don't care bit” is used herein to mean a data bit or data bit position that can have either a logic 1 or a logic 0 value, so that the value of the bit position is not important.
Given the very large number of don't care bits that can be found in the test vectors of a test data set, a significant number of test vector compression schemes have been developed, wherein a linear decompressor using only linear operations is employed to decompress the test vectors. These schemes include techniques based on linear feedback shift register (LFSR) reseeding, and combinational linear expansion circuits consisting of XOR Gates. Linear compression schemes are very efficient at exploiting don't care values in the test cubes, in order to achieve large amounts of compression. At present, virtually all available commercial tools for compressing test vectors use linear compression schemes. Test data compression reduces test costs by reducing tester storage, test time, and test data bandwidth requirements.
However, notwithstanding the benefits of currently available linear compressors, the amount of compression that can be achieved with linear compression schemes depends directly on the number of specified bits in the test vector. While linear decompressors are very efficient at exploiting don't care bits in the test data, they cannot exploit collations in the test data, and thus cannot compress the test data to less than the total number of specified bits in the test data. Accordingly, effort has been made to achieve further compression by supplementing linear schemes with non-linear compression.
In one technique, based on probability of usage, a non-linear decoder uses non-linear statistical transformations that exploit correlations in the test data, in order to reduce the number of specified bits that need to be produced by the linear decompressor. This technique is disclosed in a paper authored by Ward et al, and entitled “Using Statistical Transformations to Improve Compression for Linear Decompressors”, 20th IEEE International Symposium on Defect and Fault Tolerance (VLSI Systems), pages 42-50, 2005 (hereinafter “Ward publication”) This paper was co-authored by one of the inventors named herein. However, such technique is limited to a single set of correlated data. Also, while meritorious, the technique requires an iterative procedure that could involve substantial complexity. It would be desirable to provide a method of non-linear compression that was significantly simpler, and yet achieved the goal of reducing the number of specified bits that must be produced by the compressor.